The design of a complex analog, mixed-signal, or RF IC is a large undertaking involving a design team which may include system designers, digital designers, analog designers, and a chip level implementation team. Distinct and separate from the design team may be a verification team, whose sole focus is to check the work of the design team. In general, when designing any large, complex system, a distinct and separate verification task may become necessary when the complexity of what is being designed increases to a point where the designer or designers may no longer be able to adequately check their own work. In digital IC design, this point occurred in the mid 1990's. The design of complex analog, mixed-signal, and RF ICs has now reached this point. Design bugs or errors now occur in the analog section, in the interface between the analog and digital section, and in the digital section that works closely with the analog. The root causes for these errors include miscommunication between the design teams, incorrect interpretation of the design specifications, incorrect or incomplete design specifications, and simple human error. It is these symptoms that suggest that a distinct and separate analog verification task may be necessary.
Analog, mixed-signal, and RF designs begin with the creation of at least one specification for the design. Typically, there is a plurality of specifications for a design. Depending on the design team, specifications may be formal and detailed, or these specifications may be as informal as a set of handwritten notes. Regardless, there are specifications that represent some level of understanding of what the analog design is to do as agreed to with the end user of the design. A typical flow is that from the specifications, the designers implement the design. When completed, the design is translated to layout. The layout is checked to match the design and to be design rule correct. If there is digital layout, the analog layout is then combined with the digital layout. Additional checks are conducted on the final layout. Once all of the checks pass, the design is released to manufacturing. After manufacturing, each chip is tested to validate that they are working.
Designs may be implemented hierarchically where there is a top or a chip level comprising blocks or components. The design may be implemented starting from the top, starting from the blocks, or both. The blocks, components, top-level, and chip-level have ports consisting of inputs, outputs, and bidirectional signals that facilitate communication from one part of the design to another.
The purpose of analog verification is to validate that the analog design meets its specifications, that the analog is properly connected to the rest of the design, and that in conjunction with the register transfer logic (“RTL”) that has been developed, that the IC behaves correctly. A key technology used when verifying designs is the use of computer simulators. Computer simulators allow the designer or verification engineer to predict what the design will do prior to manufacturing the design. A limitation of computer simulations is that simulations may be very time consuming. At present, simulating the analog section with all of the transistors with the rest of the IC is prohibitive, because the simulations times are too long. These simulation times may range from weeks to months. Even simulating the analog section alone may be prohibitive. To address this issue, analog verification relies on a model representation of the design and the design components. This is often referred to as a behavioral model. Behavioral models, when written properly, simulate much faster than the design. To use this model, however, it is critical that the model be proven to match the design implementation. If the model does not match the design, there is no certainty as to whether or not the design is truly being verified. To verify the consistency of the model and the design, a self checking regression test is applied independently to the model and the design. The regression tests apply stimulus to either the model or the design and checks the outputs of what is being tested. The expected outputs are determined by the specifications. If the actual outputs match the expected outputs, then to what the regression tests are applied and specifications are consistent. If both the model and design are consistent with the specifications, then the model and design are consistent, and therefore, the model, the design, and the specifications are consistent.
Analog verification is a new field in which there is little automation. Datasheets, reports, models, regression tests, netlists that combine blocks together, connect modules, symbols, and simulation scripts are usually written manually. Designers and verification engineers typically use templates or files written for a previous project as a starting point to gain efficiency. Of the automation that does exist in the field of analog verification, most fall under the categories of formal techniques, model generation, and testbench generation with most of the work in model generation.
In all fields of study, there is much literature on model generation, essentially the idea of building an abstract representation of something detailed. However, different techniques are required for different disciplines. For example, in the field of electronic design automation of which aiding in the design of analog, mixed-signal, and RF ICs is a part, there are techniques for the generation of digital models, digital system level models, and transistor device level models. U.S. Pat. No. 5,363,320 to Graeme Boyle, Susan Bergquist, Ernest McReynolds, and Matson Haug (1993) describes an approach to device or component level modeling. Devices include transistors, resistors, capacitors, and inductors. The creation of a behavioral model of an analog block which is a combination of devices requires different techniques in that abstraction or the removal of detailed behavior is required. One of the primary goals of having an analog model is that it simulate faster than a complete description of the design. The goal of device modeling is to have a very accurate representation of the devices where detailed behavior is included. U.S. Pat. No. 5,463,563 to Owen Bair, Patrick Yin, and Chih-Chung Chen (1995) describes an automatic modeling approach for logic, a subset of digital. The focus is on generating accurate timing information. Since analog signals fundamentally differ from digital signals, this work cannot be applied to creating analog behavioral models. Digital signals have a fixed number of values, usually two, on or off. Analog signals are continuous and may take on any value within a range. As a result, different modeling techniques are required. Also, simulating analog signals may require a different simulator, and therefore, different types of models. An event-driven simulator is typically used to simulate digital designs. Simulating analog signals often requires a simulator have an ordinary differential equation solver engine. This type of engine is known as a SPICE engine or an analog simulator. A SPICE engine requires solving a network of simultaneous equations. Simulators that have both an event-driven simulation engine and SPICE engine are generally known as AMS simulators or mixed-signal simulators. Modeling languages targeted for analog include Verilog-A, Verilog-AMS, and VHDL-AMS. Custom language extensions to Verilog and SystemVerilog have also been written to extend an event-driven engine to be able to accommodate some amount of analog modeling. Analog modeling may be accomplished using a digital language, but in many circumstances, an analog modeling language or a digital language with custom extensions is required. Model generation techniques in other fields, such as digital, do not use analog modeling languages nor do they use custom analog extensions to a digital language.
In the field of analog model generation, two basic approaches have been proposed. The first is based on an abstract description of the design such as a specification or equations representing the function that the design is to perform, and the second is based on the implementation of the design itself The latter requires that the design be completed before the model can be created. “Simulation-based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing” by Walter Daems, Georges Gielen, and Willy Sansen presented at the IEEE/ACM International Conference on Computer Aided Design in 2001 describes a technique to create signomial and posynomial performance models based on SPICE or circuit simulation of the implementation of the design to be modeled. “First Steps Towards SAT-based Formal Analog Verification” by Saurabh Tiwary, Anubhav Gupta, Joel Phillips, Claudio Pinello, Radu Zlatanovici presented at The IEEE/ACM International Conference on Computer Aided Design in 2009 describes an alternative method for analog verification. In both cases the implementation of the design in the form of a netlist of all of the devices and how these devices interconnect is required.
For the model generation approaches that begin with an abstract description of the design, the prior art for this approach may be broken into two types of methods. The first is circuit type based, where specific knowledge of the type of analog, mixed-signal, or RF circuit being modeled needs to be pre-written into the tool generating the models. This knowledge may be in the form of equations or templates for the models where typically all that is required of the user is to enter parameters for the type of circuit. Often, model templates or equations specific to the circuit type are build into the tool. “Automatic Analog Model Generation for Behavioral Simulation” by Brian Antao and Fatehy El-Turky presented at the IEEE Custom Integrated Circuits Conference in 1992 discusses the generation of behavioral models for s-domain and z-domain filters. The input to the model generator are the coefficients for the filters. In this case, specific domain knowledge about s-domain and z-domain filters, two types of circuits, are pre-programmed into the generator. “A Formal Approach for Specification-Driven AMS Behavioral Model Generation” by Subhankar Mukherjee, Antara Ain, S Panda, Rejdeep Mukhopadhyay, and Pallab Dasgupta presented at the Design, Automation, and Test in Europe Conference in April, 2009 describes a method in which the user enters specifications including the type of circuit being modeled to generate behavioral models. In this paper, the authors use as an example to describe their approach, a low drop out (LDO) regulator and explain how domain knowledge for LDOs is included in their tool. US Patent Application Publication 2008/0048675 by Edouard Ngoya and Jean Rousset (published 2008) describes a method to accurately create a noise model in RF circuits. This is focused on analyzing a specific class of circuits, RF oscillators, RF mixers, and RF amplifiers, where built in knowledge of these types of circuits are required. This publication is also more of an analysis technique and not a method for generating a behavioral model of a design. The second type of the description based approaches to model generation is to enter a description of the design using a schematic capture tool or topology editor tool. U.S. Pat. No. 5,963,724 to H. Alan Mantooth, Christopher Wolff (1999) provides an example of this approach.
U.S. Pat. No. 5,369,604 to Naiknaware Ravindranath, G. N. Nandakumar, and Srinivasa Kasa (1994) describes an approach for automatic test plan generation. The invention described in U.S. Pat. No. 5,369,604 requires a circuit description, functional models, test models, and heuristic rules to generate the test plan.